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PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
Rev. 02 -- 8 June 2006 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
1.2 Features
I Logic level compatible I Low gate charge
1.3 Applications
I DC-to-DC converters I Switched-mode power supplies
1.4 Quick reference data
I VDS 30 V I RDSon 17 m I ID 43.4 A I Ptot 57.6 W
2. Pinning information
Table 1. Pin 1 2 3 mb Pinning Description gate (G) drain (D) source (S) mounting base; connected to drain
G
[1]
Simplified outline
mb mb
Symbol
D
2 1 3 123
mbb076
S
SOT428 (DPAK)
[1]
SOT78 (3-lead TO-220AB)
It is not possible to make a connection to pin 2 of the SOT428 package.
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2. Ordering information Package Name PHD36N03LT PHP36N03LT DPAK SC-46 Description plastic single-ended surface-mounted package; 3 leads (one lead cropped) plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB Version SOT428 SOT78 Type number
4. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage drain-gate voltage (DC) gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C Tmb = 25 C; pulsed; tp 10 s Tmb = 25 C; VGS = 10 V; see Figure 2 and 3 Tmb = 100 C; VGS = 10 V; see Figure 2 Tmb = 25 C; pulsed; tp 10 s; see Figure 3 Tmb = 25 C; see Figure 1 Conditions 25 C Tj 175 C 25 C Tj 175 C; RGS = 20 k Min -55 -55 Max 30 30 20 43.4 30.7 173.6 57.6 +175 +175 43.4 173.6 Unit V V V A A A W C C A A
Source-drain diode
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
2 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
120 Pder (%) 80
03aa16
120 Ider (%) 80
03aa24
40
40
0 0 50 100 150 Tmb (C) 200
0
0
50
100
150
200 Tmb (C)
P tot P der = ----------------------- x 100 % P tot ( 25C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature
103 ID (A) 102 Limit RDSon = VDS / ID
ID I der = ------------------- x 100 % I D ( 25C ) Fig 2. Normalized continuous drain current as a function of mounting base temperature
001aae811
tp = 10 s
100 s 10 DC 1 ms
1 1 10 VDS (V)
102
Tmb = 25 C; IDM is single pulse; VGS = 10 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
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Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4. Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min [1] [1]
Symbol Parameter thermal resistance from junction to ambient SOT78 SOT428
Typ 60 75 50
Max 2.6 -
Unit K/W K/W K/W K/W
thermal resistance from junction to mounting base see Figure 4 vertical in free air minimum footprint SOT404 minimum footprint
-
[1]
Mounted on a printed-circuit board; vertical in still air.
10 Zth(j-mb) (K/W) = 0.5 1 0.2 0.1 0.05 10-1 0.02
P
001aae810
=
tp T
single pulse
tp t T
10-2 10-5
10-4
10-3
10-2
10-1 tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
4 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5. Characteristics Tj = 25 C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 A; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 250 A; VDS = VGS; see Figure 9 and 10 Tj = 25 C Tj = 175 C Tj = -55 C IDSS drain leakage current VDS = 24 V; VGS = 0 V Tj = 25 C Tj = 175 C IGSS RDSon gate leakage current drain-source on-state resistance VGS = 20 V; VDS = 0 V VGS = 4.5 V; ID = 12 A; see Figure 6 and 8 Tj = 25 C Tj = 175 C VGS = 10 V; ID = 25 A; see Figure 6 and 8 VGS = 3.5 V; ID = 5.2 A; see Figure 6 and 8 Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf VSD total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage IS = 25 A; VGS = 0 V; see Figure 13 VDS = 15 V; RL = 0.6 ; VGS = 10 V; RG = 10 VGS = 0 V; VDS = 25 V; f = 1 MHz; see Figure 14 ID = 36 A; VDS = 15 V; VGS = 10 V; see Figure 11 and 12 18.5 4.2 2.9 690 160 110 6 10 33 19 0.97 1.2 nC nC nC pF pF pF ns ns ns ns V 18 32.4 14 22 22 39.6 17 40 m m m m 0.05 10 1 500 100 A A nA 1 0.5 1.5 2 2.2 V V V 30 27 V V Conditions Min Typ Max Unit
Source-drain diode
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
5 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
30 ID (A) 20
001aae812
10
4.5
3.8
3.5
40 RDSon (m)
001aae813
3.4 VGS (V) = 3.4 3.5 30 3.8 3.0 20 2.8 4.5 10 10
3.2
10 2.6 VGS (V) = 2.4
0 0 0.2 0.4 0.6 0.8 1.0 VDS (V)
0 0 10 20 30 ID (A) 40
Tj = 25 C
Tj = 25 C
Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values
40 ID (A) 30
001aae814
Fig 6. Drain-source on-state resistance as a function of drain current; typical values
2 a 1.5
03af18
20
1
10 175 C Tj = 25 C
0.5
0 0 1 2 3 VGS (V) 4
0 -60
0
60
120
Tj (C)
180
Tj = 25 C and 175 C; VDS > ID x RDSon
R DSon a = ----------------------------R DSon ( 25C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature
Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
6 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
2.5 VGS(th) (V) 2 max
03aa33
10-1 ID (A) 10-2
03aa36
1.5
typ
10-3 min typ max
1
min
10-4
0.5
10-5
0 -60
10-6 0 60 120 Tj (C) 180 0 1 2 VGS (V) 3
ID = 1 mA; VDS = VGS
Tj = 25 C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of junction temperature
10 VGS (V) 8
001aae817
Fig 10. Sub-threshold drain current as a function of gate-source voltage
VDS ID VGS(pl)
6
4 VGS(th) 2 VGS QGS1 0 0 5 10 15 QG (nC) 20 QGS2 QGD QG(tot)
003aaa508
QGS
ID = 36 A; VDS = 15 V
Fig 11. Gate-source voltage as a function of gate charge; typical values
Fig 12. Gate charge waveform definitions
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
7 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
40 IS (A) 30
001aae815
104 C (pF) 103
001aae816
Ciss 20 Coss Crss
102 10 175 C Tj = 25 C
0 0 0.3 0.6 0.9 VSD (V) 1.2
10 10-1
1
10 VDS (V)
102
Tj = 25 C and 175 C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain voltage; typical values
Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
8 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428
y E b2 A A1 A E1
mounting base D1 HD
D2
2 L2 1 3
L L1
b1 e e1
b
w
M
A
c
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.93 0.46 b 0.89 0.71 b1 1.1 0.9 b2 5.46 5.00 c 0.56 0.20 D1 6.22 5.98 D2 min 4.0 E 6.73 6.47 E1 min 4.45 e 2.285 e1 4.57 HD 10.4 9.6 L 2.95 2.55 L1 min 0.5 L2 0.9 0.5 w 0.2 y max 0.2
OUTLINE VERSION SOT428
REFERENCES IEC JEDEC TO-252 JEITA SC-63
EUROPEAN PROJECTION
ISSUE DATE 06-02-14 06-03-16
Fig 15. Package outline SOT428 (DPAK)
PHD_PHP36N03LT_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
9 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78
E p
A A1 q
D1
mounting base
D
L1
L2 Q
L
b1
1
2
3
b c
e
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.7 4.1 A1 1.40 1.25 b 0.9 0.6 b1 1.45 1.00 c 0.7 0.4 D 16.0 15.2 D1 6.6 5.9 E 10.3 9.7 e 2.54 L 15.0 12.8 L1 3.30 2.79 L2 max. 3.0 p 3.8 3.5 q 3.0 2.7 Q 2.6 2.2
OUTLINE VERSION SOT78
REFERENCES IEC JEDEC 3-lead TO-220AB JEITA SC-46
EUROPEAN PROJECTION
ISSUE DATE 05-03-22 05-10-25
Fig 16. Package outline SOT78 (3-lead TO-220AB)
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
10 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 6. Revision history Release date 20060608 Data sheet status Product data sheet Change notice Supersedes PHD36N03LT-01 Document ID PHD_PHP36N03LT_2 Modifications:
* *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Addition of PHP36N03LT Product data -
PHD36N03LT-01 (9397 750 11613)
20030630
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
11 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V.
10. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
PHD_PHP36N03LT_2
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 -- 8 June 2006
12 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 8 June 2006 Document identifier: PHD_PHP36N03LT_2

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